BCD low noise high sensitivity charge detection amplifier for high performance image sensors

ABSTRACT

The image sensor charge detection amplifier has a charge storage well  60 , a charge sensor  32  for sensing charge levels in the charge storage well  60 , a charge drain  28  adjacent to the charge storage well  60 , and charge transfer structures for transferring charge from the charge storage well  60  to the charge drain  28.

REFERENCE TO RELATED APPLICATIONS

This is a Divisional of application Ser. No. 08/299,686, filed Sept. 01,1994, U.S. Pat. No. 5,546,438, issued Aug. 13, 1996, which is aDivisional application of Ser. No. 08/087,645, filed Oct. 7, 1993,issued as U.S. Pat. No. 5,369,047 on Nov. 29, 1994.

The following co assigned patent application is incorporated herein byreference: U.S. Ser. No. 08/048,038 Filing Date Apr. 14, 1993 TI CaseNo. TI-17677.

FIELD OF THE INVENTION

This invention generally relates to image sensor devices and moreparticularly to charge coupled devices.

BACKGROUND OF THE INVENTION

Without limiting the scope of the invention, its background is describedin connection with charge coupled device (CCD) image sensors, as anexample. Essential to good low noise performance of a CCD image sensoris the charge detection amplifier which converts charge stored at anindividual photo site into a signal of adequate magnitude for furtherprocessing.

The most popular charge detection concept in CCD sensors is based on afloating diffusion circuit. A typical prior art charge detectionamplifier consists of a floating diffusion detection node and anamplifier circuit. See Hynecek, J., “Method of Making Top Buss VirtualPhase Frame Interline Transfer CCD Image Sensor”, U.S. Pat. No.5,151,380, issued Sep. 29, 1992. The charge detection node is aconventional gated floating diffusion structure typically used withvirtual phase CCDs and has an externally driven reset gate.

SUMMARY OF THE INVENTION

Generally, and in one form of the invention, the image sensor chargedetection amplifier has a charge storage well, a charge sensor forsensing charge levels in the charge storage well, a charge drainadjacent to the charge storage well, and charge transfer structures fortransferring charge from the charge storage well to the charge drain.

This invention provides several advantages. One advantage is that acomplete reset of the structure is accomplished. There is no charge leftin the detection well after the reset. Another advantage is thatcomplete reset means no kTC noise. This leads to lower noise performanceand simpler signal processing. Another advantage is the non destructivecharge readout. Since no charge is lost in the detection node, it can betransferred to another CCD stage. Another advantage is that thisinvention is a smaller structure than prior structures because the MOStransistor and the detection well are integrated into one device. Thesmaller structure leads to higher sensitivity which is also desirable.Another advantage is that additional internal or external circuits canbe easily connected to this detection amplifier to increase the gain, toobtain gamma correction, or to obtain nonlinear signal compression whichextends the dynamic range.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a cross-section of a first preferred embodiment low noise highsensitivity charge detection amplifier;

FIG. 2 is a diagram of the potential wells created by the device of FIG.1;

FIGS. 3-5 show the device of FIG. 1 at three stages of fabrication;

FIG. 6 is a simplified circuit diagram of the low noise high sensitivitycharge detection amplifier with a source bias;

FIG. 7 is a circuit diagram of a first preferred embodiment positivefeedback circuit for a low noise high sensitivity charge detectionamplifier;

FIG. 8 is a wave form diagram of the inputs and the output of thecircuit of FIG. 7;

FIG. 9 is a circuit diagram of a circuit for generating the reset signalfrom the serial register signal.

FIG. 10 is a circuit diagram of a second preferred embodiment positivefeedback circuit for a low noise high sensitivity charge detectionamplifier;

FIG. 11 is a cross-section of a second preferred embodiment low noisehigh sensitivity charge detection amplifier;

Corresponding numerals and symbols in the different figures refer tocorresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 is a cross-section of a first preferred embodiment of a low noisehigh sensitivity charge detection amplifier for high performance imagesensors. The device is called a bulk charge detector (BCD) because thecharge detection in this device can be viewed as detection of chargepresent in the bulk silicon under the P channel MOS structure. Thestructure of FIG. 1 includes a P type silicon substrate 20, an N typelayer 22 in the substrate 20, P+ virtual phase regions 24 and 26 formedin the upper portion of N type layer 22, P+ source 32 formed in theupper portion of N type layer 22, gate insulator layer 34, transfer gate36, transistor gate 40, donor implants 42 in the N type layer 22, donorimplant 43 below virtual phase region 26, and N+ drain 28. Drain 28 canbe replaced with another transfer gate similar to gate 36 in FIG. 1 oranother CCD structure.

The operation of the device of FIG. 1 will be described below and isillustrated by the potential profile shown in FIG. 2, directly below thecorresponding regions of the device of FIG. 1. These regions are giventhe following names: P+ regions 24 and 26 are called virtual gates (orvirtual electrodes) and also serve as a drain for the active transistor,the region below the virtual gate 24 is called a virtual barrier, theregion below virtual gate 26 is called a virtual well, the region belowtransfer gate 36 and below donor implant 42 is called a clocked well,the region below the transfer gate 36 and not below donor implant 42 iscalled a clocked barrier, and the region below the transistor gate 40 isthe transistor gate well.

FIGS. 3-5 illustrate successive steps in a process for fabricating a lownoise high sensitivity charge detection amplifier element according tothe preferred embodiment, as shown in FIG. 1. Referring first to FIG. 3,an N type layer 22 is formed in P type semiconductor substrate 20. Ntype layer 22 may be formed by ion implantation. A dopant such asphosphorus may be used as the implant dopant. Then a gate insulatorlayer 34 is formed over the surface of the device. The gate insulatorlayer 34 is preferably formed of oxide and may be grown from thesubstrate. Next, a photoresist layer is used to pattern an implant intoN type layer 22 to form the donor implants 42 shown in FIG. 3. Thisimplant is done with an N type dopant such as arsenic or phosphorous.After the photoresist layer is stripped, another photoresist layer isused to pattern an implant into N type layer 22 to form N+ drain 28,shown in FIG. 3. This implant is also done with an N type dopant such asphosphorous or arsenic. In case of a non destructive readout, the drainis replaced by another CCD structure.

After the photoresist layer is stripped, the transistor gate 40 and thetransfer gate 36 are deposited, doped to be conductive, patterned, andetched, as shown in FIG. 4. The transistor gate 40 and the transfer gate36 can be polysilicon, in which case they may be doped in place by adopant such as phosphoric oxy trichloride (POCI₃). Next, the transistorgate 40 and the transfer gate 36 are used for a self-alignedimplantation step to form P+ source 32 and P+ drain regions (virtualphase regions) 24 and 26, as shown in FIG. 5. This implant is done witha P type dopant such as boron. The region 32 may be doped separatelyfrom regions 24 and 26. Then a photoresist layer may be used to patternan implant to form the donor implants 43 shown in FIG. 1. Alternatively,the donor implants 43 can be made in a self aligned manner. This implantis done with an N type dopant such as phosphorous.

The detection structure shown in FIG. 1 is an enclosed gate P-channelMOS transistor. Hole current is injected from the source 32 and flowsinto the P+ drains 24 and 26. The gate 40 of the device is kept at asuitable potential to form a well 60, shown in FIG. 2, for collection ofcharge underneath. As charge is transferred into this well 60, thetransistor threshold is changed and this is sensed at the source 32.After the sensing is completed, signal charge is transferred out of thetransistor gate well 60 by pulsing the transistor gate 40 negative.Charge is transferred out of the transistor gate well 60, through thevirtual well 64, and into charge drain 28, or in the case of continuingCCD structures, into the clocked barrier and clocked well of the nextCCD stage.

The operation of the device of FIG. 1 is explained by referring to thepotential profile shown in FIG. 2. The energy levels for an electron inthe buried channel (conduction band minimum) are shown for the variousregions of the device and for different bias levels of the transfer gate36, and different bias levels of the transistor gate 40. Starting withan electron in the clocked barrier 50 at level 51 below transfer gate 36with the transfer gate bias approximately equal to substrate bias, theoperation is as follows. First the electron falls into the clocked well54 at level 55. The electron will remain in the clocked well 54 as longas the transfer gate bias is approximately equal to substrate biasbecause the potential wells of both adjacent regions are at a lowerpotential. When the transfer gate 36 is switched to a negative bias withrespect to the substrate 20, the potential level of the clocked well 54changes to level 57 and the potential level of clocked barrier 50changes to level 53. As a result, the electron passes from the clockedwell 54 to the virtual barrier 58. The electron then moves from thevirtual barrier 58 into the transistor gate well 60 at level 63 wherethe presence of charge is detected through sensing the potential of thesource 32.

For reset, the transistor gate bias returns to a more negative voltagewhich changes the potential level of transistor gate well 60 from level63 to level 61. As a result, the electron passes from the transistorgate well 60 to the virtual well 64. The electron then moves into thecharge drain 28 where it is removed. The electron can also continue intoanother gate similar to gate 36 for non destructive sensing. Chargeremoval from the well 60 is called reset. This reset process provides acomplete charge removal from the structure because there is no chargeremaining in the transistor well 60 after the charge is transferred tothe charge drain 28 or to the next CCD stage.

A simplified circuit diagram of the first preferred embodiment of thelow noise high sensitivity charge detection amplifier is depicted inFIG. 6 and incorporates the structure of FIG. 1. The circuit includestransfer gates 80, 82, 84, and 86, active transistor 88, transistordrain 90, transistor gate 92, transistor source 94, current source 96,and charge drain 98. The current source 96 provides current to thesource 94 which flows to the drain 90.

The transistor is a P-channel MOS device with enclosed source 32 anddrain common to virtual phase regions 24 and 26. If the source 32 isbiased by a constant current source 96 from a power supply, thepotential of the source 32 will adjust itself to a level which will besensitive to charge in the transistor region. This is similar to bulkcharge modulated device (BCMD) operation, which is described in Hynecek,J., “Bulk Charge Modulated Transistor Threshold Image Sensor Elementsand Method of Making”, U.S. Pat. No. 4,901,129, issued Feb. 13, 1990.The P-channel transistor operates in a source follower mode with thegate-source threshold determined by the doping profiles of the structureand by the amount of electrons under the transistor gate.

The transfer gates 80, 82, 84, and 86 make up a portion of a CCD shiftregister. The remaining portion of the CCD shift register is not shown.The CCD shift register transfers charge to the charge detectionamplifier. The structure of the transfer gates is shown by the transfergate 36, shown in FIG. 1. Charge is transferred through the shiftregister to the charge detection node by clocking the voltages on thetransfer gates and the transistor gate. Once charge is transferred intothe transistor gate well 60, charge is detected by sensing the voltageon the source 94 of transistor 88.

FIG. 7 is a diagram of a preferred embodiment positive feedback circuitfor the BCD detector of FIG. 1. The circuit includes BCD activetransistor Q₆, and transistors Q₁, Q₂, Q₃, Q₄, and Q₅. In the circuit ofFIG. 7, transistor Q₅ provides positive feedback from the output on line110 to the gate 112 of the BCD detector Q₆. This feedback increases thedetection node sensitivity several times (3 to 5 times). Transistor Q₁is a current source for bias of BCD transistor Q₆. Transistor Q₁ isconnected between a voltage source VDD and the source 114 of the BCDtransistor Q₆. Q₂ is a source follower which provides the output on line110. The gate 118 of source follower transistor Q₂ is coupled to thesource 114 of the BCD transistor Q₆. Q₄ serves as a switch to accomplishreset. A reset pulse is coupled to the gate of transistor Q₄. TransistorQ₃ is a resistive load for transistor Q₂.

Additional circuits such as that shown in FIG. 9 can be added to theamplifier of FIG. 7 to derive the reset pulse automatically from theserial register clock signal. The circuit of FIG. 9 includes transistorQ₇ and capacitor 120. The circuit of FIG. 9 generates the reset pulsefrom the leading edge of the serial register clock signal. The amplitudeof the reset pulse depends on the threshold of the transistor Q₇ and theDC level of the shift register clock signal φ_(SR).

FIG. 8 is a timing diagram showing the inputs to the device of FIG. 7.φ_(SR) is the serial register clock signal which controls the CCD shiftregister. φ_(RS) is the input to the gate 116 of transistor Q₄. V_(o) isthe output signal on line 110 in FIG. 7.

The timing cycle starts with a reset period to clear charge from the BCDtransistor well 60. For the reset period, the reset signal φ_(RS) isswitched from low to high. The high reset signal φ_(RS) turns ontransistor Q₄ which lowers the voltage on the gate 112 of BCD transistorQ₆. The lower gate voltage on Q₆ causes the transistor gate well 60 tochange to potential level 61, shown in FIG. 2. This forces charge tomove from the transistor well 60 to the charge drain 28. During thereset period, φ_(SR) is at a high voltage so that the transfer well 54is at potential level 55. The transfer well holds charge while thetransistor well 60 is being cleared of charge.

After the reset period, the reset signal is switched to a lower voltage.This turns off transistor Q₄ and allows the gate voltage on the BCDtransistor Q₆ to rise. The higher gate voltage on Q₆ creates potentialwell 60 at level 63, shown in FIG. 2. Then the BCD transistor Q₆ isready to receive charge from the shift register. The serial registerclock signal φ_(SR) is then switched to a low voltage which changes thepotential of transfer well 54 from level 55 to level 57. This causescharge in the last transfer well 54, shown in FIG. 2, to move into thetransistor well 60. When charge moves into the transistor well 60, thepotential level of the transistor well 60 changes. The potential levelof the transistor well is dependent on the amount of charge that istransferred from the last transfer well of the serial register. Thischange in potential level is sensed on the source 114 of the BCDtransistor Q₆. The dependency on the amount of charge is shown by thevariable output voltage level 130, shown in FIG. 8.

Once charge is sensed by the source of transistor Q₆, the feedback ofthe amplifier circuit of FIG. 7 increases the sensitivity of the chargedetector by changing the gate voltage on the BCD transistor Q₆ accordingto the change in the source voltage through the feedback path providedby transistor Q₅. It is also possible to replace transistor Q₅ with amore sophisticated circuit 119, shown in FIG. 10, with a nonlineartransfer characteristic. This feature can be used to increase thedynamic range of the detector by nonlinear signal compression. If thetransfer characteristic of the feedback path is properly selected, it ispossible to obtain the TV gamma correction directly at the chargedetection node.

Because of the complete charge clearing reset process of the BCDdetector, the device has no kTC noise. This leads to lower noiseperformance and simpler signal processing. Noise of the BCD detector canbe estimated by the equations below. The following equations are from asimple model for a MOS transistor:$I = {\frac{1}{2}\frac{w}{L}\mu \quad {C_{ox}\left( {V_{G} - V_{T}} \right)}^{2}}$$g_{m} = {\frac{w}{L}\mu \quad {C_{ox}\left( {V_{G} - V_{T}} \right)}}$$\frac{I}{g_{m}} = {\frac{1}{2}\left( {V_{G} - V_{T}} \right)}$

where

μ=majority carrier mobility

C_(ax)=gate capacitance per unit area

w=channel width

L=channel length

g_(m)=transconductance

Noise is given by the well known equation:$v_{n} = \sqrt{4\frac{kT}{g_{m}}f_{b}}$

By substituting for g_(m) from the transistor model above, the followingnoise equation is derived:$v_{n} = \sqrt{{\alpha 2}\quad \frac{kT}{q}\frac{{qf}_{b}}{I}\left( {V_{G} - V_{T}} \right)}$

where

kT is thermal energy.

f_(b) is frequency bandwidth.

α is a factor less than or equal to 2 used to include noise of the bias

circuit.

Typical values of the parameters are:

V_(G)−V_(T)=1V

α=2

f_(b)=10 MHz

I=20 μA

Substituting the typical values into the equation for v_(n), noise willbe v_(n)=90 μV.

Typical charge conversion sensitivity achievable with this structure is10 μV/e⁻. This leads to the noise equivalent electrons of N_(ee)=9e⁻which is a respectable value for a 10 MHz bandwidth.

In an alternative embodiment, shown in FIG. 11, another gate 140 can beadded to the circuit. The gate 140 gives more flexibility for chargetransfer from transistor well 60. Also, another complete CCD structurecan be added to the circuit of FIG. 1 in place of the charge clearingdrain 28 to facilitate non destructive readout.

This invention provides several advantages. One advantage is that acomplete reset of the structure is accomplished. There is no charge leftin the detection well after the reset. Another advantage is thatcomplete reset means no kTC noise. This leads to lower noise performanceand simpler signal processing. Another advantage is non destructivereadout capability. Another advantage is that this invention is asmaller structure than prior structures because the MOS transistor andthe detection well are integrated into one device. The smaller structureleads to higher sensitivity which is also desirable. Another advantageis that additional internal or external circuits can be easily connectedto this detection amplifier to increase the gain, to obtain gammacorrection, or to obtain nonlinear signal compression which extends thedynamic range.

A few preferred embodiments have been described in detail hereinabove.It is to be understood that the scope of the invention also comprehendsembodiments different from those described, yet within the scope of theclaims.

For example, additional circuits can be added to this amplifier toderive the reset pulse automatically from the serial register clocksignal.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

What is claimed is:
 1. An active transistor charge detection device witha positive feedback circuit comprising: an active transistor pixelcharge detection device having: a semiconductor substrate of a firstconductivity type; a semiconductor layer of a second conductivity typein the substrate; virtual phase regions of the first conductivity typeformed in the semiconductor layer, the virtual phase regions formingvirtual phase potential areas for carriers of the second conductivitytype; a transistor source region of a first conductivity type formed inthe semiconductor layer and spaced apart from the virtual phase regions;a charge drain region of a second conductivity type formed in thesemiconductor layer and spaced apart from the virtual phase regions; aninsulating layer on the semiconductor layer; a transistor gate electrodeformed on the insulating layer and located above a portion of thesemiconductor layer that surrounds the transistor source region betweenvirtual phase regions, the transistor gate electrode forming atransistor potential well for carriers of the second conductivity typein response to a voltage; a transfer gate electrode formed on theinsulating layer and separated from the transistor gate electrode by thevirtual phase regions, the transistor gate electrode located between thetransfer gate electrode and the charge drain, the transfer gateelectrode forming a transfer potential area for carriers of the secondconductivity type in response to a voltage; resetting circuitry coupledto the transistor gate electrode; amplifier circuitry coupled to thetransistor source region; and feedback circuitry coupled between anoutput of the amplifier circuitry and the transistor gate electrode forincreasing the source sensitivity.
 2. The device of claim 1 wherein theresetting circuitry is a transistor.
 3. The device of claim 1 whereinthe amplifier circuitry includes: a first transistor having a firstsource and a first gate both coupled to the transistor source region; asecond transistor having a second source and a second gate, the secondgate is coupled to the transistor source region; a third transistorhaving a drain coupled to the second source; and an output line coupledto the second source.
 4. The device of claim 1 wherein the feedbackcircuitry is a transistor.
 5. The device of claim 1 wherein the feedbackcircuitry is a circuit with nonlinear transfer characteristics.